1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device provided with a large capacity memory allowing a fast operation with a low power consumption.
2. Description of the Background Art
A conventional static semiconductor memory device 8000, which will be referred to as an "SRAM" hereinafter, will be briefly described below with reference to FIG. 23.
Conventional SRAM 8000 includes a memory cell array which is divided into a plurality of memory blocks. FIG. 23 shows one of memory blocks BKi and a structure related to the same.
In conventional SRAM 8000 shown in FIG. 23, memory block BKi includes a plurality of memory cells MC arranged in rows and columns, a plurality of bit line pairs BIT0 and /BIT0, BIT1 and /BIT1, . . . , BITn and /BITn, a plurality of word lines WL0, WL1, . . . and WLm, transfer gates 102.0, 102.1, . . . and 102.n, a data I/O line pair IO and /IO, and sense amplifiers 104 and 106.
The plurality of bit line pairs BIT0 and /BIT0, BIT1 and BIT1, . . . , and BITn and /BITn (which will be generally referred to as bit line pairs BIT and /BIT, hereinafter) are arranged correspondingly to the columns, respectively. The plurality of word lines WL0, WL1, . . . and WLm (which will be generally referred to as word lines WL, hereinafter) are arranged correspondingly to the rows, respectively.
Transfer gates 102.0, 102.1, . . . and 102.n (which will be generally referred to as transfer gates 102, hereinafter) are arranged correspondingly to the columns, respectively.
Each transfer gate 102 includes NMOS transistors N90 and N91, PMOS transistors P90 and P91, and an inverter circuit 114, and outputs a signal, which is carried on corresponding bit line pair BIT and /BIT, onto data I/O line pair IO and /IO in response to corresponding one of Y-address signals Y0, Y1, . . . and Ym (which will be generally referred to as Y-address signals Y, hereinafter).
Sense amplifiers 104 and 106 amplify the signal on data I/O line pair IO and /IO.
Referring to FIG. 23, a read operation of conventional SRAM 8000 will be described below. In the following operation, data is to be read from memory cell MC located at a crossing, e.g., between bit line pair BIT0 and BIT0 and word line WL0.
In this case, word line WL0 is set to the selected state (i.e., is raised to H-level). When word line WL0 is selected, data of memory cells MC connected to word lines WL0 is output onto corresponding bit line pairs BIT and /BIT, respectively.
Subsequently, Y-address signal Y0 is raised to H-level. Thereby, transfer gate 102.0 is activated, and the signal on corresponding bit line pair BIT0 and /BIT0 is output onto data I/O line pair IO and /IO.
Thereby, data of memory cell MC is amplified by sense amplifier 104 in the first stage and sense amplifier 106 in the second stage, and thereafter is externally output through a peripheral circuit (not shown).
FIGS. 24, 25 and 26 show structures of memory cells MC used in the conventional SRAMs. More specifically, FIG. 24 shows a structure of the memory cell of a full CMOS type, FIG. 25 shows a structure of the memory cell of a TFT load type, and FIG. 26 shows a structure of the memory cell of a high-resistance load type.
In FIG. 24, memory cell MC of the full CMOS type is formed of NMOS transistors N100, N101, N102 and N103 as well as PMOS transistors P100 and P101.
In FIG. 25, memory cell MC of the TFT load type is formed of NMOS transistors N105, N106, N107 and N108 as well as TFT elements T100 and T101.
In FIG. 26, memory cell MC of the high-resistance load type is formed of NMOS transistors N109, N110, N111 and N112 as well as resistance elements R100 and R101.
Memory cells which have recently been used in large-capacity SRAMs are miniaturized so that drive powers thereof have been reduced and, in other words, currents which can flow therethrough for output of signals onto bit lines have been reduced. This reduces speeds at which the signals are output from memory cells onto bit line pairs, and results in a tendency that a long time is required for externally outputting the read signal. This prevents a fast operation of the large-capacity SRAM, and further results in such a situation that a speed equal to that in the former generation cannot be achieved without difficult.
For compensating the drive power of the memory cell, a length of the bit line pair may be reduced for reducing a load driven by the memory cell.
According to this measure, the number of the memory cells per bit line pair (and therefore the size of the memory block) decrease. Therefore, it is necessary to increase the number of the memory blocks for ensuring a storage capacity. However, this increases the number of bit line pairs, and therefore increases the number of circuits such as load circuits and transfer gates connected to the bit line pairs, resulting in increase in chip size.
Particularly in the large-capacity SRAM, increase in chip size results in increase in cost. Therefore, mere reduction in length of the bit line pair cannot be employed.
In view of this, a column sense method may be employed as measures for reducing a load driven by the memory cell without increasing the length and number of the bit line pairs. A structure of an SRAM employing the conventional column sense method will be described below with reference to FIG. 27.
FIG. 27 shows one of memory blocks BKi and a structure related to the same in a conventional SRAM 9000 of the column sense type.
The same components as those of conventional SRAM 8000 in FIG. 23 bear the same reference numbers, and will not be described below.
Conventional SRAM 9000 of the column sense type shown in FIG. 27 employs a plurality of column sense amplifiers 108.0, 108.1, . . . and 108.n instead of sense amplifier 104 shown in FIG. 23.
Column sense amplifiers 108.0, 108.1, . . . , 108.n (which will be generally referred to as column sense amplifiers 108, hereinafter) are provided correspondingly to bit line pairs BIT and /BIT, respectively. Column sense amplifier 108 is activated in response to corresponding Y-address signal Y.
FIG. 28 is a circuit diagram showing an example of a specific structure of conventional column sense amplifier 108 shown in FIG. 27, and more specifically shows by way of example the structure of column sense amplifier 108.0. Structures of other column sense amplifiers 108 are the same as that of column sense amplifier 108.0 shown in FIG. 28.
Column sense amplifier 108.0 shown in FIG. 28 includes a load circuit 110 and an input circuit 112. Load circuit 110 includes PMOS transistors P120 and P121, and input circuit 112 includes NMOS transistors N120, N121 and N122.
PMOS transistor 120 is connected between a power supply potential and data I/O line IO, and has a gate electrode connected to data I/O line /IO. PMOS transistor P121 is connected between the power supply potential and data I/O line /IO, and has a gate electrode connected to data I/O line IO.
One of terminals of NMOS transistor N120 is connected to data I/O line IO, and the other is connected to NMOS transistor N122. One of terminals of NMOS transistor N121 is connected to data I/O line /IO, and the other is connected to NMOS transistor N122.
A gate electrode of NMOS transistor N120 is connected to corresponding bit line /BIT0. A gate electrode of NMOS transistor N102 is connected to corresponding bit line BIT0.
The other terminal of NMOS transistor N122 is connected to a ground potential. Further, NMOS transistor N122 receives corresponding Y-address signal Y0 on its gate electrode.
An operation of column sense amplifier 108.0 will be briefly described below. NMOS transistor N122 is turned on when Y-address signal Y0 attains H-level.
NMOS transistor N121 is turned on in response to a potential on bit line BIT0, and NMOS transistor N120 is turned on in response to a potential on bit line /BIT0.
When a minute potential difference occurs between bit lines BIT0 and /BIT0, a corresponding potential difference occurs between data I/O lines IO and /IO. Load circuit 110 amplifies this minute potential difference.
Owing to provision of column sense amplifiers 108 corresponding to the bit line pairs, respectively, the memory cell is not required to drive the resistance of the transfer gate and the capacity of the I/O line so that the potential on the bit line pair can be raised or lowered rapidly.
As described above, employment of conventional SRAM 9000 of the column sense type ensures a fast operation. However, provision of the column sense amplifiers for the respective bit line pairs causes unpreferable increase in chip area.
More specifically, conventional SRAM 8000 shown in FIG. 23 is provided with transfer gate 102, which is formed of four elements, for each column (bit line pair). However, conventional SRAM 9000 of the column sense type shown in FIG. 27 requires nine elements in total for column sense amplifier 108 formed of five elements and a transfer gate for writing, which has the same structure as transfer gate 102 and thus is formed of four elements, although not shown.
Measures for reducing a chip area are disclosed in "Sense Amplifier" (Japanese Patent Laying-Open No. 8-69694), which will be referred to as "Reference 1" hereinafter, and "Semiconductor Memory Device" (Japanese Patent Laying-Open No. 6-89586), which will be referred to as "Reference 2" hereinafter.
In the semiconductor memory devices disclosed in References 1 and 2, a sense amplifier load portion is commonly used in one memory block.
In the structure including memory blocks each formed of, e.g., 128 columns, the loads are reduced to 1/16 in number if 8-I/O structure is employed (i.e., each I/O is provided for 16 columns), and the loads are reduced to 1/8 in number if 16-I/O structure is employed (i.e., each I/O is provided for 8 columns).
In recent memory cell arrays, the number of bits has been increased for increase in speed and performance of CPUs and others, and it is expected that products employing 16-I/O structures and 32-I/O structures will be increasingly used. When the semiconductor memory devices disclosed in References 1 and 2 are used, it is necessary to change the number of loads in accordance with the I/O structure for maximizing the effect of reducing the area, and a single type cannot be used for various I/O structures.